一种混合晶向结构硅片研究

Vol. 32, No. 6 Journal of Semiconductors June 2011Study of hybrid orientation structure waferTan Kaizhou( 谭开洲 )1; , Zhang Jing(张静 )1, Xu Shiliu( 徐世六 )1, Zhang Zhengfan( 张正璠 )1,Yang Yonghui( 杨永晖 )2 , Chen Jun(陈俊 )2 , and Liang Tao(梁涛 )21 National Laboratory of Analog Integrated Circuits, Chongqing 400060, China2 Sichuan Institute of Solid-State Circuits, Chongqing 400060, ChinaAbstract: Two types of 5 m thick hybrid orientation structure wafers, which were integrated by (110) or (100)orientation silicon wafers as the substrate, have been investigated for 15– 40V voltage ICs and MEMS sensorapplications. They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique, andhave been presented in China for the first time. The thickness of BOX SiO2 buried in wafer is 220 nm. It has beenfound that the quality of hybrid orientation structure with (100) wafer substrate is better than that with (110) wafersubstrate by “ Sirtldefect etching of HOSW”.Key words: HOT; SOI; (110) crystal orientation; 15– 40V ICs; MEMS sensorDOI: 10.1088/1674-4926/32/6/063002 PACC: 7340T EEACC: 25001. IntroductionIt is well know that CMOS ICs are usually made from(100) crystal orientation silicon wafer, and NMOS carrier mo-bility is about 2–3 times greater than PMOS carrier mobility,but most people might forget that hole mobility in (110) orien-tation silicon wafer is about 2 times larger than that in (100)wafer, which was found by Sato et al.?1 in 1969. Many newtechnologies, such as strained silicon, have been developedas the design rule in CMOS technology scales down to the45 nm node and beyond, and high hole mobility in (110) ori-entation wafer have been recognized again. Then, hybrid ori-entation technology (HOT), where NMOS transistors are fab-ricated on (100) wafer but PMOS transistors are fabricated on(110) wafer, was exploited ?2 9 . HOT improves PMOS transis-tor performance, maintains NMOS transistor performance and,in the meantime, reduces the mismatch of PMOS and NMOStransistor characteristics. In addition, (110) wafer has a largerpiezoresistive coefficient than (111) and (100) wafer, which iswidely used for MEMS sensors. Most of the HOT active layerthickness is usually much thinner (45 – 100nm) and was usedin 90 nm CMOS node or less outside China?3; 7 , which is dif-ferent from the thickness that we use.2. Process flowThe process flow of the hybrid orientation structure wafer(HOSW) experiment is shown in Fig. 1. Both (110) and (100)wafers are 100 mm in diameter. The (110) wafer is n-type,whose resistivity is 10– 20 cm, whereas (100) wafer is alson-type, whose resistivity is 7– 10 cm.First, we must obtain hybrid orientation SOI wafer. TheseSOI wafers are made by a conventional wafer bonding, grind-ing and SOI polishing process flow, and the wafer is differentfrom the top Si layer in orientation. The (110) and (100) waferswere used as a handle wafer or a top Si layer, respectively. Theburied BOX thermal SiO2 is about 220 nm thick and the topSi layer thickness is about 3.3 – 3.62 m (Fig. 1(a)). A micro-graph of hybrid orientation SOI wafer is shown in Fig. 2. ThereFig. 1. HOSW processflow. (a) Formation of (110/100) or (100/110)hybrid orientation SOI. (b) A part of the top Si layer and BOX SiO2etching. (c) Non-selective epitaxy. (d) Silicon epitaxial layer CMP.* Project supported by the National Basic ResearchProgram of China (No. 61398) and the National Laboratory of Analog Integrated CircuitsFoundation of China (No. YZ0808).Corresponding author. Email: tkz123@163.comReceived 14 September2010, revised manuscript received 18 January 2011 c 2011 Chinese Institute of Electronics063002-1J. Semicond. 2011, 32(6) Tan Kaizhou et al.Fig. 2. Photo of hybrid orientation SOI wafer. The left SOI handlewafer orientation is (110) and the top Si layer is (100), and the rightone is (100) and (110), respectively.Fig. 3. Cross section of (110) HOSW.is no defect in the upper left corner of the left-hand SOI waferin Fig. 2 but there is a mirror reflection pattern.Second, after the photolithographic process, a part of thetop Si layer and BOX SiO2 was etched, as shown in Fig. 1(b).Then a 7.5 m thick non-selective epitaxial layer was de-posited (Fig. 1 (c)).Third, a roughly 5 m thick silicon epitaxial layer wasremoved from the epitaxial wafer by CMP (Fig. 1 (d)). ThenHOSW was carried out.3. Results and discussion3.1. Cross section of hybrid orientation structureFigure 3 shows a cross section of the hybrid orientationstructure with (110) handle wafer ((110) HOSW), and Figure 4is a cross section of the hybrid orientation structure with (100)handle wafer ((100) HOSW). From Fig. 4, it can be seen thatthere is no distinct step across (110)/(100) on wafer surface.The top Si layer on BOX SiO 2 is about 5 m thick and BOXSiO 2 thickness is about 0.22 m.3.2. Surface shape and defect indicationBoth (110) and (100) handle wafer hybrid orientationstructures had a thermal oxide, which formed in 950 ?C vaporambience, the oxide on the (100) surface is 98 nm thick, and theFig. 4. Cross section of (100) HOSW.Fig. 5. Micrograph of HOSW surface.oxide on the (110) surface is 136 nm thick. Figure 5 shows ami-crograph of the hybrid orientation structure surface. In Fig. 5,the top left image is a (110) handle wafer hybrid orientationstructure, where orientations inside and outside the rectangularpattern area are (110) and (100), respectively. However, the topright image is (100) handle wafer, where the orientations in andout of the rectangular pattern are(100) and (110), respectively.It can be seenclearly that there are many special sharp-angledcorners (shown asdashedcircles in the bottom image of Fig. 5)on (100) HOSW, but there are no such corners on (110) HOSW.A photolithographic layout schematic on wafer is shownin Fig. 6. All of the patterns in the layout are rectangular.To know what the surface quality of HOSW looks like, thewafer has been smashed by natural cleavage fracture. We puta suitable sized fragment into “ Sirtl ”etching solution (CrO 3 :H2O : HF = 50 g : 100 mL : 100 mL) for about 2 min andthen took it out to take a micrograph. It was found that (110)HOSW had some different behavior from (100) HOSW. First,the cleavage plane angle was about 60? in (110) HOSW (seeFig. 7), but it was 90? in (100) HOSW (see Fig. 8).Second, there were some line defects on the surface of(110) HOSW, indicated by dashed ellipses in Fig. 7. There werealmost no defects on (100) HOSW except for some along theedgeof the fragment, asshown on the right part of Fig. 8. These063002-2J. Semicond. 2011, 32(6) Tan Kaizhou et al.Fig. 6. Layout schematic on wafer.Fig. 7. Surface micrograph after (110) HOSW cleavage.defects along the edge were probably caused by cleavage frac-ture mechanical stress.4. ConclusionsTwo types of 5 m thick hybrid orientation structures wererealized mainly by SOI wafer bonding, non-selective epitaxyand CMP, and they have been presented in China for the firsttime. “ Sirtldefect etching ”of HOSW indicated that the qual-ity of hybrid orientation structure with (100) wafer substrate isbetter than that with (110) substrate.AcknowledgmentsThe authors would like to thank Li Zhilang, Wang Bing,Chen Guangbing, Wang Jianan, Xu Xueliang, Li Kaicheng andFig. 8. Surface micrograph after (100) HOSW cleavage.Cao Yang for their support and helpful discussions.References[1] SatoT, Takeishi Y, Hara H. Effects of crystallographic orientationon mobility, surface state density, and noise in p-type inversionlayers on oxidized silicon surfaces. Jpn J Appl Phys, 1969, 8(5):588[2] Fischetti M, Ren Z, Solomon P,et al. Six-band kp calculation ofthe hole mobility in silicon inversion layers: dependenceon sur-face orientation, strain, and silicon thickness. J Appl Phys, 2003,94(2): 1079[3] Yang M, Ieong L, Shi K, et al. High performance CMOS fabri-cated on hybrid substrate with different crystal orientations. In-ternational Electron Devices Meeting, 2003: 453[4] Nakamura H, Ezaki T, Iwamoto T, et al. Effects of selecting chan-nel direction in improving performance of sub-100nm MOSFETsfabricated on (110) surface Si substrate. Jpn J Appl Phys, 2004,43(4B): 1723[5] Mizuno T, Sugiyama N, Tezuka T, et al. (110)-surface strained-SOI CMOS technology. IEEE Trans Electron Devices, 2005,52(3): 367[6] Stathis JH, Bolam R, Yang M, et al. Interface stategeneration inpFETswith ultra-thin oxide andoxynitride on (100) and (110) Sisubstrates.Microelectron Eng, 2005, 80(1): 126[7] Sung C Y, Yin H, Ng H Y. High performance CMOS bulk tech-nology using direct silicon bond (DSB) mixed crystal orientationsubstrates.International Electron Devices Meeting, 2005: 225[8] Yang M, Chan V W C, Chan K K, et al. Hybrid-orientation tech-nology (HOT): opportunities and challenges. IEEE Trans Elec-tron Devices, 2006, 53(5): 965[9] Krishnamohan T, Kim D, Thanh V D. Double-gate strained-Geheterostructure tunneling FET (TFET) with record high drivecurrents and 60 mV/dec subthreshold slope. InternationalElectron Devices Meeting, 2008: 1063002-3