SERIS-Rolf STANGL

1SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Double-sided passivated contacts for n-type mono-silicon solar cells with large-area cell efficiency potential 23% Rolf STANGL, Puqun WANG, Ranjani SRIDHARAN, Zheng XIN, Zhi Peng LING* Solar Energy Research Institute of Singapore (SERIS) *now at REC Solar, Singapore SNEC conference, Shanghai, China 3-6th June, 2019 2SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Front PECVD passivation/ARC stack Screen-printed and fired front metal contact Diffused emitter Screen-printed and fired rear metal contact Rear PECVD passivation n+:poly-Si Interfacial oxide SERIS’ monoPolyTM cells Rear-side n+:poly-Si deposition Voc (mV) Jsc (mA/cm2) FF (%) Efficiency (%) PECVD (SERIS + Meyer Burger) 697 41.4 81.3 23.5 LPCVD (SERIS) 681 39.9 81.2 22.2 Main loss: front contact recombination monoPoly ➔ biPoly J0,cont-front = 750 fA cm-2 J0,pass-front = 31 fA cm-2 J0,cont-rear = 250 fA cm-2 J0,pass-rear = 5.2 fA cm-2 (96%) (4%) (96%) (4%) Σ 60 fA cm-2front Σ 15 fA cm-2rear 3SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Outline ❑ Vision: Double-sided contact passivated solar cells Moving from SERIS’ monoPolyTM to biPolyTM ❑ Requirements/Challenges for biPolyTM cells ➢ Ultra-thin (front-side) poly-Si layers ➢ Suited metallization for those layers ❑ Development of ultra-thin contact passivation layers ➢ Etch-back ➢ Process re-optimization for ultra-thin layers ❑ Metallization schemes for ultra-thin contact passivation layers ➢ Screen printing on TCO ➢ (Inline plating) ❑ Efficiency potential for biPoly (using our current LPCVD layers) ❑ Summary & Conclusion 4SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Motivation The beauty of contact passivation Measured PL image Conventional rear-contact Contact passivated rear-contact n-diffused Si SiOx tunnel layer (TL)n+-poly Si capping layer (CL) 5SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Motivation (cont’d) Simulated parasitic absorption in LPCVD poly-Si layers Vary poly-Si thickness SiOx TLp +-poly-Si CL SiOx TLn+-poly-Si CL Vary front ❑ poly-Si thickness reduction (250 nm ➔ 10 nm) ❑ Current loss (parasitic abs.) - rear-side: 0.4 mA cm-2 (max) - front-side: (old LPCVD nk-data) 10nm LPCVD: ~2 mA/cm2 10nm PECVD: a bit less Vary rear SunSolveTM simulations (in air) 0.4 ➔ ultra-thin front poly-Si required! 6SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). ❑ Processing of ultra-thin ( 100nm n+-poly-Si) Contacting “thin” 50nm poly-Si) punch through punch through SEM picture 10SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Metallization schemes for thin poly-Si ❑ It is possible to contact poly-Si layers by means of TCO (without significant loss in lifetime) ❑ These TCO layers can be subsequently low-T screen printed Screen printing, contacting TCO on top of ultra-thin poly-Si layers 11SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Metallization schemes for thin poly-Si ❑ Minor iVoc to Voc loss after TCO deposition & low-T screen printing ❑ Efficiency for 50 nm front-side LPCVD poly-Si: 19.4% ❑ Device integration for 10 nm front-side poly-Si currently on-going (mask removal issues encountered) Screen printing, contacting TCO on top of ultra-thin poly-Si layers biPoly 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 5 10 15 20 25 30 35 40 current density j [ mA/cm 2 ] voltage [ V] 50 nm fro nt po ly -Si ( n + ) 25 0 n m fro nt po ly -Si ( n + ) 12SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Efficiency potential for biPolyTM cells Based on measured J0 and Rc values of our SiOx/LPCVD-poly-Si layers Calculated efficiency potential ultra-thin SiOx/poly-Si layers ( fix front-contact properties vary rear-contact j0,rear, Rc,rear ) 22.3 % (full-area rear-contact) 23.2 % (localized rear-contact) Corresponding studies for our SiOx/PECVD-monoPoly layers on-going! 13SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Summary biPoly cells work ❑ Efficiency potential: - Using our developed “ultra-thin” LPCVD contact passivation layers (10 nm front-side textured n+-poly, 10 nm rear-side planar p+-poly) ➔ Efficiency potential of biPoly exceeds monoPoly by 1% absolute Challenges to be overcome ❑ biPoly cells require: - ultra-thin front-side poly-Si layers ( 10nm) - suited metallization schemes, contacting these layers ❑ Etch-back technology enables ultra-thin poly-Si layers (3 nm) ❑ TCO layers on top of poly-Si: promising metallization scheme ❑ Currently mask removal issues in case of ultra-thin layers 14SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Thank you for your attention! rolf.stangl @nus.edu.sg We are also on: 15SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). Metallization schemes for thin poly-Si Inline plating (1) Using fs laser ablation to create damage-free contact openings (2) Ag inline plating to form front- contacts on-going fs laser Having to solve screen printing on p+-poly-Si layers! 16SERIS is a research institute at the National University of Singapore (NUS). SERIS is supported by the National University ofSingapore (NUS), National Research Foundation Singapore (NRF) and the Singapore Economic Development Board (EDB). ❑ Rear-side poly-Si thickness reduction (250 nm ➔ 25 nm) ❑ Maximum current gain ~0.4 mA/cm2 Motivation (cont’d) Simulated parasitic absorption in rear-side LPCVD poly-Si Ellipsometry SunSolveTM simulations Vary rear poly-Si thickness